1. Field of the Invention
The present invention is related generally to a memory array and specifically to PMOS NAND gate structure.
2. Description of Related Art
A conventional NAND stack ROM includes numerous strings of series connected N-channel bit transistors such as EEPROM storage cells. FIG. 1 shows such a string 10 having eight N-channel storage cells 12a-12h interposed between an N-channel string select transistor 14 and an N-channel ground select transistor 16. String select transistor 14 is coupled between cells 12a-12h and bit line BL of its associated NAND stack array (not shown for simplicity) and has a gate coupled to receive a control signal SS1. Ground select transistor 16 is coupled between cells 12a-12h and ground potential and has a gate coupled to receive a control signal GS1. Typically, each of cells 12a-12h is of a conventional stacked-gate NMOS EEPROM cell structure formed in a common P-well 18, as shown in FIG. 2, having N+ source 20 and drain 22 regions, a floating gate 24, and a control gate 26. The sources of each of cells 12a-12h and select transistors 14, 16 are tied together, as indicated by a common source node 17 in FIG. 1. The control gate of each of cells 12a-12h is coupled to receive a respective one of control signals CG1-CG8.
String 10 may be programmed in either bit, byte, or page mode and may be erased in bulk mode. Referring to FIGS. 1 and 2, to program for instance cell 12h, the gate of string select transistor 14 and common source 17 are pulled to 5V while P-well 18, the gate of ground select transistor 16, and bit line BL are held at ground potential. Cells 12a-12g are turned on by pulling signals SS1 and CG1-CG7 to approximately 12V, thereby pulling drain 22 of cell 12h to 0V. Control gate 26 of cell 12h is pulled to approximately 19V via signal CGS, thereby charging floating gate 24 of cell 12h via electron tunneling. In this manner, the threshold voltage V.sub.T of cell 12h is increased from approximately -2V (in its erased state) to approximately 0.7-1.4 V (in its programmed state).
To read cell 12h, bit line BL is pulled to 3V while common source 17 and P-well 18 are held at ground potential. String select transistor 14, ground select transistor 16, and cells 12a-12g are turned on via the application of 5V to signal lines SS1, GS1, and CG1-CG7, respectively, while control gate 26 of cell 12h is held at ground potential. In this manner, cell 12h will turn off, and thus string 10 will not conduct current, only if floating gate 24 of cell 12h is programmed.
Cells 12a-12h of string 10 are erased in bulk by applying 20V to P-well 18 while bit line BL, common source 17, and the gate of ground select transistor 16 are floating. Signals CG1-CG8 are held at ground, thereby causing electron tunneling from floating gate 24 to P-well 18 of each of respective cells 12a-12h. Typical operating ranges for the bias conditions described above are listed below in Table 1, where cell 12h is the selected cell.
TABLE 1 ______________________________________ Program Un- selected Node Erase Data 0 Bit line Read ______________________________________ Bit-Line Floating 0 V 5 V 3 V CS1 0 V 5 V 5 V 5 V CG1 0 V 12 V 12 V 5 V CG2 0 V 12 V 12 V 5 V CG3 0 V 12 V 12 V 5 V CG4 0 V 12 V 12 V 5 V CG5 0 V 12 V 12 V 5 V CG6 0 V 12 V 12 V 5 V CG7 0 V 12 V 12 V 5 V CG8 0 V 19 V 19 V 0 V CG1 Floating 0 V 0 V 5 V Common Floating 5 V 5 V 0 V Source P-Well 20 V 0 V 0 V 0 V ______________________________________
Cells 12a-12h require high programming and erase voltages and also suffer from read disturb as a result of hot carriers injected into floating gate 24 of cells 12a-12h during read operations. It would thus be desirable to form a NAND stack array which requires less programming and erase voltages, is capable of higher read currents, and which does not suffer from read disturb problems.